1. Field of the Invention
This invention relates to electronic devices and, in particular, to multiple lead electronic devices.
2. Art Background
The enhancement of device density in integrated circuits (ICs) has seen rapid progress. This increase in density has caused a concomitant increase in the number of leads associated with the IC. Indeed, integrated circuits having up to 256 leads are readily available. These leads are dedicated for chip drivers (IC circuit output which drive external interconnections), ground returns, power and other signals. Typically, these leads, 10 emanating from the silicon chip (FIGS. 1 and 2) or multichip modules 60 (FIG. 3) and terminating at a lead frame as shown at 20 in FIG. 1 or on a circuit board, 30 in FIGS. 2 and 3, are spaced a minimum of 0.004 inches and are at smallest 0.001 inches in diameter and 0.10 inches in length. Generally, these connections from the silicon to the lead frame or circuit board are made by wire bonding--a process that entails thermosonic bonding of the leads to pads. Lead lengths attainable with conventional technology such as lead bonding because of mechanical constraints, are unlikely to be reduced much below 0.04 inches. Nevertheless, there is a strong desire to reduce lead length since this results in reduced lead inductance.
An A.C. signal generated by a chip driver and returning on one or more ground leads produces a potential difference across the common ground leads. (An A.C. signal includes digital signal information.) For integrated circuits with a large number of chip drivers which rapidly switch in the same direction (e.g. 16 chip drivers switching in 1 ns and even more significantly 32 chip drivers switching in 1 ns), the combined effect of this induced ground potential difference (sometimes referred to as ground bounce) or inductive noise is significant. That is, an induced transient potential difference occurs between the ground plane 42 (FIG. 4) present in teh driver integrated circuit 45 and the ground plane 41 associated with interconnects (e.g. printed wiring boards, PWBs) that provide electrical communication between these integrated circuits. This significant difference in potential between ground planes produces errors in information processing. Inductive noise of the power leads is of less concern because by-pass capacitors can be applied very close to the chips to help reduce power fluctuations.
The difference in ground potential is proportional to the rate of change of driver current, the number of chip drivers switching, the combined ground return (including via 43, the ground plane, 41, ground via 70, ground lead 10, and via 44) inductance, and inversely proportional to the number of ground returns. (See A. J. Rainal, AT&T Bell Laboratories Technical Journal, January 1984.) Thus, the induced ground potential becomes larger and errors become more frequent with increased current rate of change which in turn increases with increases in data rate or decreases in rise time, T.sub.r, increases in the current difference, .DELTA.I, incurred during the rise time and increases in the number of chip driver leads N.sub.d. Generally, for .DELTA.I N.sub.d /T.sub.r values above 16 ma per ns, error rates become significant and for values above 32 ma per ns become of even greater concern. (For analog signals, a similar figure of merit is appropriate. If IC's having both analog and digital circuitry, errors from the digital component generally predominate.)
A variety of approaches has been employed to reduce inductive noise, (also denominated ground bounce, simultaneous switching noise, or delta I noise). For example, non-linear circuitry has been proposed in U.S. Pat. No. 4,398,106. Additionally, solder bump leads have been proposed, at least in part, to reduce inductance. In this approach, small nodes of solder are present on the integrated circuit at each electrical connection point. Corresponding nodes of solder (or bare contact pads) are present on the printed wiring board. Alignment and reflow of the solder bumps produce a plurality of relatively low inductance connections. However, the use of solder bumps and other relatively recent technology is substantially more expensive than conventional wire bonding and has not achieved the reliability of wire bond technology. Since wire bonding is a mature and reliable technology with a large capital investment, it is quite desirable to reduce the inductive noise and retain the wire bond technology.